In the manufacturing of integrated circuits, many lithography processes are involved to define the patterns of the components of the integrated circuits. The lithography processes typically involve applying a photo resist on a wafer, placing a mask covering the photo resist, wherein the mask contains desirable patterns, exposing the photo resist to light, and developing the photo resist. With the mask containing the patterns, some regions of the photo resist are exposed to the light, while other regions are not exposed. The exposed (or non-exposed) regions of the photo resist can thus be removed, and hence the patterns of the mask are transferred to the photo resist.
The design of the patterns on the mask often involves logic operations, during which patterns of some components are generated based on the design of other components of the integrated circuits. For example, the pattern of source and drain regions of a transistor may be formed using a logic operation “DIFFUSE BOOLEAN NOT POLY,” which means that the source and drain regions may be generated by deducting the poly regions from the diffusion regions.
Conventional logic operations, however, suffer from limitations. For example, FIG. 1 illustrates the layout of two transistors, PMOS transistor 2 and NMOS transistor 12. PMOS transistor 2 includes diffusion region 6 and gate poly 4. NMOS transistor 12 includes diffusion region 16 and gate poly 14. The patterns of stressed contact etch stop layer (CESL) 8 and 18 are formed by performing logic operations to the patterns of PMOS transistor 2 and NMOS transistor 12, respectively. For example, by expanding the pattern of diffusion regions 6 and 16 by a constant distance ΔX in one direction and a constant distance ΔY in another direction. To avoid design problems, in the conventional logic operations, CESLs 8 and 18 were spaced apart from each other to ensure that conventional design rules are followed.
The performance of PMOS device 2 and NMOS device 12 are related to the sizes of CESLs 8 and 18. However, in the conventional mask design, the sizes of CESLs 8 and 18 are not flexible even if there are additional spaces for increasing their sizes. Therefore, the device performance improvement that would have been obtained was not achieved. New logic operation methods are thus needed.